The present invention relates generally to computer systems and, more particularly, to methods and apparatus for operating computer systems in a manner to ensure that only up-to-date data are used in the computer systems.
Traditionally, computer systems have included a central processing unit or CPU, data storage devices including a main memory which is used by the CPU for performance of its operations and a system bus which interconnects the CPU to the main memory and any other data storage devices. I/O devices also are connected to a system via the bus. The bus thus serves as a communications link among the various devices making up a computer system by carrying clock and other command signals and data signals among the devices. A cache memory can be inserted between the main memory and the CPU to speed up memory operations which are traditionally slow in comparison to the operating speed of the CPU.
To further expand the operating speed and capacity of computer systems, systems including multiple processors and/or multiple system buses have been developed. Additional expansion is possible by the use of subsystem I/O buses which typically are coupled to the system bus or buses to connect additional devices or agents to the computer system. These additional resources can be used by the computer system and thereby expand the processing capabilities of the system. The addition of a subsystem I/O bus is advantageous since it presents only one load for the system bus or buses yet provides system access to a number of agents. If the agents are directly coupled to the system bus, they load the system bus with a load per device, such as eight or sixteen bus loads, as opposed to the single bus load presented by the subsystem I/O bus.
Additional improvements of the operating speed and capacity of computer systems can be made by buffering data exchanges between agents on a subsystem I/O bus and main memory on the system bus. By buffering these data exchanges, agents on the subsystem bus can operate at their full speed without being delayed by having to wait for data exchanges which are carried out at speeds slower than their normal operating speeds. Unfortunately, the inclusion of buffered subsystem I/O buses, cache memories and other operation enhancing devices in high performance computer systems can present system operating problems.
For example, in a computer system including a cache memory, a subsystem I/O bus with buffered data exchanges with main memory and an interrupt system which does not require ownership of either the system or I/O buses, i.e. a "tightly-coupled" interrupt system, an agent on the I/O bus can perform a buffered memory write and issue an interrupt to the processor indicating the write to main memory is complete The processor may then issue an interrupt acknowledge cycle and retrieve an interrupt vector from the interrupt system before the buffered data has actually been transferred to main memory. Thus, because the buffered data was not written to main memory, the processor will be operating with main memory data which is not up-to-date.
It is thus apparent that there is a need for improved methods and apparatus for operating a computer or processing system to ensure that only up-to-date data is used in the processing system.